CameraLink v2.0版本英文版协议规范，已去除文档保护密码，方便大家使用

该模块主要根据被测FPGA发来的图像地址信号将DDR2中的指定图像数据读取出来，并且分五路发送给CameraLink接口，由CameraLink图像采集卡接收并传给上位机显示。

CameralinkHS协议详细说明

Camera-Link-v2.0-Feb10-2012-final-cameralink标准协议

Camera Link_v2.0 协议英文原版

Camera Link_v1 协议版本

英国active silicon，是成像产品和嵌入式视觉系统制造商。Active silicon成立于1988年， ActiveSilicon产品为嵌入式视觉系统，自动变焦/对焦相机（以及相关数据转换卡）， 图像采集卡。产品主要面向科学和工业的领域，包括制造、生命科学、医学成像、安全和防御，太空任务，工业视觉系统的大规模部署，为客户提供相关的解决方案。

The DS90CR287 transmitter converts 28 bits of • 20 to 85 MHz Shift Clock Support LVCMOS/LVTTL data into four LVDS (Low Voltage • 50% Duty Cycle on Receiver Output Clock Differential Signaling) data streams. A phase-locked • 2.5 / 0 ns Set & Hold Times on TxINPUTs transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the • Low Power Consumption transmit clock 28 bits of input data are sampled and • ±1V Common-Mode Range (around +1.2V) transmitted. • Narrow Bus Reduces Cable Size and Cost The DS90CR288A receiver converts the four LVDS • Up to 2.38 Gbps Throughput data streams back into 28 bits of LVCMOS/LVTTL • Up to 297.5 Mbytes/sec Bandwidth data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per • 345 mV (typ) Swing LVDS Devices for Low EMI LVDS data channel. Using a 85 MHz clock, the data • PLL Requires no External Components throughput is 2.38 Gbit/s (297.5 Mbytes/sec). • Rising Edge Data Strobe This chipset is an ideal means to solve EMI and • Compatible with TIA/EIA-644 LVDS Standard cable size problems associated with wide, high-speed • Low Profile 56-Lead TSSOP Package TTL interfaces.

cameralink_v2.0_cn.pdf

Dalsa Cameralink相机采集代码，可供参靠，包括AOI的使用.....