This document presents an overview of Universal Serial Bus 3.0 architecture and key concepts. USB 3.0 is similar to earlier versions of USB in that it is a cable bus supporting data exchange between a host computer and a wide range of simultaneously accessible peripherals. The attached peripherals share bandwidth through a host-scheduled protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. USB 3.0 utilizes a dual-bus architecture that provides backward compatibility with USB 2.0. It provides for simultaneous operation of SuperSpeed and non-SuperSpeed (USB 2.0 speeds) information exchanges. This chapter is organized into two focus areas. The first focuses on architecture and concepts related to elements which span the dual buses. The second focuses on SuperSpeed specific architecture and concepts. Later chapters describe the various components and specific requirements of SuperSpeed USB in greater detail. The reader is expected to have a fundamental understanding of the architectural concepts of USB 2.0. Refer to the Universal Serial Bus Specification, Revision 2.0 for complete details.
2022-01-21 19:35:31 3.74MB USB 3.0
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AirPlay 协议规范
2022-01-21 12:02:18 357KB airplay
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PCI Express™ Card Electromechanical Specification Revision 1.1
2022-01-21 11:00:24 1.37MB Electrome chanical PCIE
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This document provides the architectural specification of the OpenCAPI data link layer (DL and DLX).
2022-01-20 22:45:24 245KB TL
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pcie base Specification 3.0 清晰
2022-01-18 21:20:02 3.92MB pcie base Specification 3.0
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SBOL规范 该存储库包含SBOL数据模型的主规范文档,格式为LaTeX。更新规范的工作流程是在主数据库上克隆,编辑和提交请求请求。 SBOL开发社区的成员可以使用问题跟踪器来标记现有规范中的问题,并查看正在考虑的正在进行中的问题。 提交对规范的更改 在撰写不重要更改的文字之前,请通过讨论将其批准为“问题”和/或“ SEP”。 建议的更改应使用适当的版本宏进行标记。为此提供了LaTeX命令\threezeroone 。有关正确用法,请参见LaTeX源中的示例。 建议的更改应在GitHub的分支或单独的fork中进行。为此,请遵循标准的git分支或分支过程。 这是实现此目的的git命令示例: git clone https://github.com/SynBioDex/SBOL-specification.git cd SBOL-specification # Make sure no
2022-01-17 10:52:40 3.88MB TeX
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DDR4 SDRAM Registered DIMM Design Specification, DDR4服务器内存条Jedec标准设计规范
2022-01-16 17:10:23 320KB DDR4 Registered DIMM Dram
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TM Forum文档 Product Catalog Management API REST Specification
2022-01-15 16:23:41 1.46MB api
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CAN Specification 2.0 The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed realtime control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors, anti-skid-systems, etc. are connected using CAN with bitrates up to 1 Mbit/s. At the same time it is cost effective to build into vehicle body electronics, e.g. lamp clusters, electric windows etc. to replace the wiring harness otherwise required. The intention of this specification is to achieve compatibility between any two CAN implementations. Compatibility, however, has different aspects regarding e.g. electrical features and the interpretation of data to be transferred. To achieve design transparency and implementation flexibility CAN has been subdivided into different layers according to the ISO/OSI Reference Model:
2022-01-14 19:23:35 162KB CAN Specification 2.0
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Dual Wire CAN Physical Layer and Data Link Layer Specification
2022-01-14 14:29:34 383KB can
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