SystemVerilog 3.1a 语言参考手册（中文版）

作者以一个使用者的身份介绍如何开发验证环境，里面列出了很多的规则和方法，国内有中文版本的。个人感觉还是英文的描述比较好...

对sv的有较深入的解读，同时推sv的验证平台做了介绍

Ashok B. Mehta (auth.) - SystemVerilog Assertions and Functional Coverage_ Guide to Language, Methodology and Applications-Springer International Publishing (2016)

SystemVerilog for Verification A Guide to Learning the Testbench Language Features Second Edition

该文档为Verilog与SystemVerilog编程陷阱 如何避免101个常犯的编码错误中文版，还算是份不错的参考资料，感兴趣的可以下载看看，

verilog编写testbench国外经典教材 Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog. It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.