classic book for Set Theory

计算 CLEAN 和 NOISY 信号之间的平均对数光谱距离。 可以选择仅在语音活动期间计算此距离。 您也可以选择一个频率范围来研究子带中的距离。

具有模态指标的随机子空间识别，包括一致模式指标和模态参与因子。 该函数不使用系统识别工具箱函数n4sid。 示例文件用于识别受高斯白噪声激励的 2DOF 系统，并为激励和响应增加了不确定性（也是高斯白噪声）。 函数 [Result]=SSID(output,fs,ncols,nrows,cut) 输入： output：输出数据大小（输出通道数，数据数） fs：采样频率ncols：hankel矩阵的列数（大于数据数的2/3） nows：hankel矩阵中的行数（超过20*模式数） cut：截止值=2*模式数 输出： 结果：结构由以下组件组成 Parameters.NaFreq : 自然频率向量Parameters.DampRatio : 阻尼比向量Parameters.ModeShape : 模式形状矩阵 Indicators.EMAC : 扩展模态幅度相干性Indicators.M

Brownian dynamics serve as mathematical models for the diffusive motion of mi- croscopic particles of various shapes in gaseous, liquid, or solid environments. The renewed interest in Brownian dynamics is due primarily to their key role in molec- ular and cellular biophysics: diffusion of ions and molecules is the driver of all life. Brownian dynamics simulations are the numerical realizations of stochastic differential equations (SDEs) that model the functions of biological microdevices such as protein ionic channels of biological membranes, cardiac myocytes, neuronal synapses, and many more.

它以教学法描述了金融中最重要的随机过程，尤其是马尔可夫链，布朗运动和mar。 它还显示了如何在财务模型的框架中理解诸如过滤，伊藤引理或吉萨诺夫定理之类的数学工具。

Differential Evolution A Practical Approach to Global Optimization 差分进化算法

Representation of Events in Nerve Nets and Finite Automata.pdf

This, Reader, is an honest book. It warns you at the outset that it is not a treatise on stochastic volatility. Nor is it a mathematical nance textbook – there are treatises and textbooks galore on the shelves of bookshops and university libraries. Rather, my intention has been to explain how stochastic volatility – and which kind of stochastic volatility – can be used to address practical issues arising in the modeling of derivatives. Modeling in nance is an engineering eld: while our task as engineers is to frame problems in mathematical terms and solve them using sophisticated machinery whenever necessary, the problems themselves originate in the form of embarrassingly practical trading questions.

有限状态机（Finite State Machine）是一种时序机，它源自于人们将一个复杂的问题分割成多个简单的部分来处理的思想。状态机通过时钟驱动下的有多个状态，以及状态之间的跳转规则来实现复杂的逻辑，一旦当前的状态确定，也就明确了相关的输入输出。 有限状态机主要分为两个类型：第一类，如果输出只和当前状态有关而和输入无关，称之为Moore状态机；第二类，输出不仅和当前状态有关也和输入有关，称之为Melay型状态机。本节将主要介绍这两类状态机、状态编码以及使用VHDL和Verilog语言描述的设计范例。

2007年五星书 英文版 Digital Design (Verilog): An Embedded Systems Approach Using Verilog Product Description Digital Design: An Embedded Systems Approach Using Verilog provides a foundation in digital design for students in computer engineering, electrical engineering and computer science courses. It takes an up-to-date and modern approach of presenting digital logic design as an activity in a larger systems design context. Rather than focus on aspects of digital design that have little relevance in a realistic design context, this book concentrates on modern and evolving knowledge and design skills. Hardware description language (HDL)-based design and verification is emphasized--Verilog examples are used extensively throughout. By treating digital logic as part of embedded systems design, this book provides an understanding of the hardware needed in the analysis and design of systems comprising both hardware and software components. Includes a Web site with links to vendor tools, labs and tutorials. Presents digital logic design as an activity in a larger systems design context. Features extensive use of Verilog examples to demonstrate HDL usage at the abstract behavioural level and register transfer level, as well as for low-level verification and verification environments. Includes worked examples throughout to enhance the reader's understanding and retention of the material. Companion Web site includes links to CAD tools for FPGA design from Synplicity, Mentor Graphics, and Xilinx, Verilog source code for all the examples in the book, lecture slides, laboratory projects, and solutions to exercises. Paperback: 584 pages Publisher: Morgan Kaufmann (September 14, 2007) Language: English ISBN-10: 0123695279 ISBN-13: 978-0123695277 contents c h a p t e r 1 Introduction and Methodology . . . . . . . . . . . 1 1.1 Digital Systems and Embedded Systems . . . . . . . . . . . . . . . . . 1 1.2 Binary Representation and Circuit Elements . . . . . . . . . . . . . 4 1.3 Real-World Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.2 Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.3 Static Load Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3.4 Capacitive Load and Propagation Delay . . . . . . . . . 15 1.3.5 Wire Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.6 Sequential Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3.8 Area and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.1 Embedded Systems Design . . . . . . . . . . . . . . . . . . . 31 1.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 c h a p t e r 2 Combinational Basics . . . . . . . . . . . . . . . . . . 39 2.1 Boolean Functions and Boolean Algebra . . . . . . . . . . . . . . . . 39 2.1.1 Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.1.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.3 Verilog Models of Boolean Equations . . . . . . . . . . . 51 2.2 Binary Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.2.1 Using Vectors for Binary Codes . . . . . . . . . . . . . . . . 56 2.2.2 Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3 Combinational Components and Circuits . . . . . . . . . . . . . . . 62 2.3.1 Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . 62 2.3.2 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.3 Active-Low Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4 Verification of Combinational Circuits . . . . . . . . . . . . . . . . . . 74 2.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 c h a p t e r 3 Numeric Basics . . . . . . . . . . . . . . . . . . . . . . . 87 3.1 Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.1.1 Coding Unsigned Integers . . . . . . . . . . . . . . . . . . . . 87 3.1.2 Operations on Unsigned Integers . . . . . . . . . . . . . . 92 3.1.3 Gray Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.2 Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.2.1 Coding Signed Integers . . . . . . . . . . . . . . . . . . . . . . 119 3.2.2 Operations on Signed Integers . . . . . . . . . . . . . . . . . 122 3.3 Fixed-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.1 Coding Fixed-Point Numbers . . . . . . . . . . . . . . . . . 131 3.3.2 Operations on Fixed-Point Numbers . . . . . . . . . . . . 136 3.4 Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.4.1 Coding Floating-Point Numbers . . . . . . . . . . . . . . . 138 3.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 c h a p t e r 4 Sequential Basics . . . . . . . . . . . . . . . . . . . . . . 151 4.1 Storage Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.1.1 Flip-flops and Registers . . . . . . . . . . . . . . . . . . . . . . 151 4.1.2 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.1.3 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.2 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.3 Sequential Datapaths and Control . . . . . . . . . . . . . . . . . . . . . 175 4.3.1 Finite-State Machines . . . . . . . . . . . . . . . . . . . . . . . 179 4.4 Clocked Synchronous Timing Methodology . . . . . . . . . . . . . . 187 4.4.1 Asynchronous Inputs . . . . . . . . . . . . . . . . . . . . . . . . 192 4.4.2 Verification of Sequential Circuits . . . . . . . . . . . . . . 196 4.4.3 Asynchronous Timing Methodologies . . . . . . . . . . . 200 4.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 4.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 c h a p t e r 5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.2 Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.2.1 Asynchronous Static RAM . . . . . . . . . . . . . . . . . . . 220 5.2.2 Synchronous Static RAM . . . . . . . . . . . . . . . . . . . . . 222 5.2.3 Multiport Memories . . . . . . . . . . . . . . . . . . . . . . . . 229 5.2.4 Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.2.5 Read-Only Memories . . . . . . . . . . . . . . . . . . . . . . . 235 5.3 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . 240 5.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 5.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 c h a p t e r 6 Implementation Fabrics . . . . . . . . . . . . . . . . . 249 6.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 6.1.1 Integrated Circuit Manufacture . . . . . . . . . . . . . . . . 250 6.1.2 SSI and MSI Logic Families . . . . . . . . . . . . . . . . . . . 252 6.1.3 Application-Specific Integrated Circuits (ASICs) . . . 255 6.2 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . 258 6.2.1 Programmable Array Logic . . . . . . . . . . . . . . . . . . . 258 6.2.2 Complex PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 6.2.3 Field-Programmable Gate Arrays . . . . . . . . . . . . . . 263 6.3 Packaging and Circuit Boards . . . . . . . . . . . . . . . . . . . . . . . . 269 6.4 Interconnection and Signal Integrity . . . . . . . . . . . . . . . . . . . . 272 6.4.1 Differential Signaling . . . . . . . . . . . . . . . . . . . . . . . . 276 6.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 c h a p t e r 7 Processor Basics . . . . . . . . . . . . . . . . . . . . . . 281 7.1 Embedded Computer Organization . . . . . . . . . . . . . . . . . . . . 281 7.1.1 Microcontrollers and Processor Cores . . . . . . . . . . . 283 7.2 Instructions and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.2.1 The Gumnut Instruction Set . . . . . . . . . . . . . . . . . . 287 7.2.2 The Gumnut Assembler . . . . . . . . . . . . . . . . . . . . . . 296 7.2.3 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . 298 7.2.4 Other CPU Instruction Sets . . . . . . . . . . . . . . . . . . . 300 7.3 Interfacing with Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 7.3.1 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 7.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 7.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 c h a p t e r 8 I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . 315 8.1 I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 8.1.1 Input Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 8.1.2 Output Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 8.2 I/O Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 8.2.1 Simple I/O Controllers . . . . . . . . . . . . . . . . . . . . . . 331 8.2.2 Autonomous I/O Controllers . . . . . . . . . . . . . . . . . 335 8.3 Parallel Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.3.1 Multiplexed Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.3.2 Tristate Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 8.3.3 Open-Drain Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.3.4 Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 8.4 Serial Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.4.1 Serial Transmission Techniques . . . . . . . . . . . . . . . . 353 8.4.2 Serial Interface Standards . . . . . . . . . . . . . . . . . . . . 357 8.5 I/O Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 8.5.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 8.5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 8.5.3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 8.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 8.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 c h a p t e r 9 Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . 379 9.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 9.2 Case Study: Video Edge-Detection . . . . . . . . . . . . . . . . . . . . . 386 9.3 Verifying an Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 9.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 9.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 c h a p t e r 1 0 Design Methodology . . . . . . . . . . . . . . . . . . 423 10.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 10.1.1 Architecture Exploration . . . . . . . . . . . . . . . . . . . . . 425 10.1.2 Functional Design . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.1.3 Functional Verification . . . . . . . . . . . . . . . . . . . . . . 429 10.1.4 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.1.5 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 10.2 Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 10.2.1 Area Optimization . . . . . . . . . . . . . . . . . . . . . . . . . 442 10.2.2 Timing Optimization . . . . . . . . . . . . . . . . . . . . . . . . 443 10.2.3 Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . 448 10.3 Design for Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 10.3.1 Fault Models and Fault Simulation . . . . . . . . . . . . . 452 10.3.2 Scan Design and Boundary Scan . . . . . . . . . . . . . . . 454 10.3.3 Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . 458 10.4 Nontechnical Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 10.5 In Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 10.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 10.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466