vhdl设计FPGA读写DS18B20温度传感器quartus工程源码+文档说明
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ds18B20 is
port(
clk : in std_logic;---50MHz
rst_n: in std_logic; --复位信号输入
one_wire : inout std_logic; --DS18B20数据线
----------------
dataout : out std_logic_vector(7 downto 0); --数码管数据输出
en : out std_logic_vector(3 downto 0)); --数码管位选信号
end ds18B20;
architecture Behavioral of ds18B20 is
signal dataout_buf:std_logic_vector(3 downto 0);
signal count:std_logic_vector(17 downto 0); --分频计数器
signal cnt_scan:std_logic_vector(17 downto 0); --数码管的扫描显示计数器
signal clk_1us:std_logic;-- 1MHz 时钟
signal cnt_1us:integer range 0 to 750002;-- 1us延时计数子
signal cnt_1us_clear:std_logic;-- 请1us延时计数子
TYPE STATE_TYPE is (S00,S0,S1,S2,S3,S4,S5,S6,S7,
WRITE0,WRITE1,WRITE00,WRITE01,READ0,READ1,READ2,READ3); --状态机
signal state: STATE_TYPE; --初始状态设置为复位状态
signal one_wire_buf:std_logic;-- One-Wire总线 缓存寄存器
signal temperature_buf:std_logic_vector(15 downto 0);-- 采集到的温度值缓存器(未处理)
signal DS18B20_DATA_buf:std_logic_vector(15 downto 0);-- 采集到的温度值缓存器(未处理)
signal DS18B20_DATA_buf_temp:std_logic_vector(15 downto 0);-- 采集到的温度值缓存器(未处理)
signal step:integer range 0 to 50;--子状态寄存器 0~50
signal bit_valid:integer range 0 to 15;--有效位
signal one_wire_in:std_logic;
signal t_buf:std_logic_vector(15 downto 0);
signal t_buf_temp:std_logic_vector(15 downto 0);
signal cnt:integer range 0 to 50;-- 计数子
-- //++++++++++++++++++++++++++++++++++++++
-- // 分频器50MHz->1MHz 开始
-- //++++++++++++++++++++++++++++++++++++++
begin
-- process (clk,rst_n)
-- begin
-- if rising_edge(clk) then
-- if(rst_n='0') then
-- cnt <= 0;
-- else
-- if(cnt = 49)then
-- cnt <= 0;
-- else
-- cnt <= cnt + 1;
-- end if;
-- end if;
-- end if;
-- end Process;