Sequential Logic and Verilog HDL Fundamentals discusses the analysis and synthesis of synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995.The book concentrates on sequential logic design with a focus on the design of various Verilog HDL projects. Emphasis is placed on structured and rigorous design principles that can be applied to practical applications. Each step of the analysis and synthesis procedures is clearly delineated. Each method that is presented is expounded in sufficient detail with accompanying examples. Many analysis and synthesis examples use mixed-logic symbols incorporating both positive- and negative-input logic gates for NAND (not AND) and NOR (not OR) logic, while other examples utilize only positive-input logic gates. The use of mixed logic parallels the use of these symbols in the industry.The book is intended to be a tutorial, and as such, is comprehensive and self-contained. All designs are carried through to completion?nothing is left unfinished or partially designed. Each chapter contains numerous problems of varying complexity to be designed by the reader using Verilog HDL design techniques. The Verilog HDL designs include the design module, the test bench module that tests the design for correct functionality, the outputs obtained from the test bench, and the waveforms obtained from the test bench.Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL with numerous design examples to help the reader thoroughly understand this popular hardware description language. The book is designed for practicing electrical engineers, computer engineers, and computer scientists; for graduate students in electrical engineering, computer engineering, and computer science; and for senior-level undergraduate students.,解压密码 share.weimo.info

非常好的资料！电子版的，我有书，但带着不方便！

Verilog HDL数字设计与综合（第二版）.pdf

基于FPGA实现Costas环的集成开发环境、Verilog HDL开发语言,,科斯塔斯环，载波同步，FPGA，数字通信，Verilog基于FPGA实现Costas环的集成开发环境、Verilog HDL开发语言,,科斯塔斯环，载波同步，FPGA，数字通信，Verilog基于FPGA实现Costas环的集成开发环境、Verilog HDL开发语言,,科斯塔斯环，载波同步，FPGA，数字通信，Verilog基于FPGA实现Costas环的集成开发环境、Verilog HDL开发语言,,科斯塔斯环，载波同步，FPGA，数字通信，Verilog

Pipeline-processor：基于Verilog HDL的五级流水线处理器 开发平台 VIVADO 16、xilinx FPGA开发板 设计要求 设计一个 5 级流水线的 MIPS 处理器，采用如下方法解决竞争问题: 采用完全的 forwarding 电路解决数据关联问题。 对于 Load use 类竞争采取阻塞一个周期 + Forwarding 的方法解决。 对于分支指令在 EX 阶段判断（提前判断也可以），在分支发生时刻取消 ID 和 IF 阶段的两条指令。 对于 J 类指令在 ID 阶段判断，并取消 IF 阶段指令。 分支和跳转指令做如下扩充：分支指令（ beq 、 bne 、 blez 、 bgtz 、 bltz) 和跳转指令 (j 、 jal 、 jr 、 jalr) 该处理器支持未定义指令异常和中断的处理 设计定时器外设，可以根据设定周期产生外部中断，通过该定时器触发

描述 流水线 CPU 设计、Quartus 平台、Verilog HDL、团队合作 用 Verilog 编写的 MIPS CPU 的实现。 该项目处于非常早期的阶段，目前仅实现 MIPS CPU 的最基本功能。 32 位 MIPS 处理器 在 Verilog 中实现 5级流水线 静态分支未采用分支预测器 解码中的分支检测（阶段 2） 支持停顿，避免写后读（RAW）等危害 可以从内存转发（第 4 阶段）和写回（第 5 阶段） 要求 该项目需要一个 Verilog 模拟器，例如 Quartus。 作者 徐东李千克 版权 版权所有 :copyright: 2014, Rui-Yi Zhang, Dong Xu, Qian-Ke Li。 版权所有。 该项目是免费软件，在下。

《设计与验证Verilog HDL》_吴继华_光盘资料

基于verilog HDL编写的分别显示个位和十位的十二进制加法计数器，压缩包里有vwf时序波形和最简单的testbench测试代码

CAM的Verilog HDL实现，个人已用quartus产品验证可行性

VerilogHDL教程-初级篇.ppt