GITHUB上一个非常好用的SPI开源代码,代码风格极好,注释清晰,结构简单,使用方便,初学者可以作为学习参考,有Verilog和VHDL两个版本。
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// Note: i_Clk must be at least 2x faster than i_SPI_Clk
//
// Parameters: SPI_MODE, can be 0, 1, 2, or 3. See above.
// Can be configured in one of 4 modes:
// Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
// 0 | 0 | 0
// 1 | 0 | 1
// 2 | 1 | 0
// 3 | 1 | 1
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// Control/Data Signals,
input i_Rst_L, // FPGA Reset
input i_Clk, // FPGA Clock
// TX (MOSI) Signals
input [7:0] i_TX_Byte, // Byte to transmit on MOSI
input i_TX_DV, // Data Valid Pulse with i_TX_Byte
output reg o_TX_Ready, // Transmit Ready for next byte
// RX (MISO) Signals
output reg o_RX_DV, // Data Valid pulse (1 clock cycle)
output reg [7:0] o_RX_Byte, // Byte received on MISO
// SPI Interface
output reg o_SPI_Clk,
input i_SPI_MISO,
output reg o_SPI_MOSI
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