老外的8051单片机的IP核，verilog源码，在quartus中综合通过，供学习或工程开发使用，很有参考价值！

his ninth edition of Digital Electronics: A Practical Approach with VHDLprovides the fundamentals of digital circuitry to students in engineering and technology curric- ula. The digital circuits are introduced using fixed-function 7400 ICs and evolve into FPGA (Field Programmable Gate Arrays) programmed with VHDL (VHSIC Hardware Description Language). (Note:Those schools not wishing to develop logic using VHDL and FPGAs can completely skip those sections of the textbook without affect- ing the continuity of the remainder of the text, which describes logic design and imple- mentationusing 7400-series ICs.) Coverage begins with the basic logic gates used to perform arithmetic operations and proceeds through sequential logic and memory circuits used to interface to mod- ern PCs. Professor Kleitz uses his vast experience of teaching electronics online and in class from his best-selling textbooks to know what it takes for an entry-level student to be brought up to speed in this emerging field. It was important to design this new text- book to present practical examples, be easy to read, and provide all of the information necessary for motivated students to teach themselves this new subject matter. This makes it ideal for learning in an online environment as well as from conventional in- class lectures. Digital electronic ICs (integrated circuits) and FPGAs are the “brains” behind common microprocessor-based systems such as those found in automobiles, personal computers, and automated factory control systems. The most exciting recent develop- ment in this field is that students now have the choice to design, simulate, and imple- ment their circuits using a programming language called VHDL instead of wiring individual gates and devices to achieve the required function. Each topic area in this text consistently follows a very specific sequence of steps, making the transition from problem definition, to practical example, to logic IC imple- mentation, to VHDL and FPGA implementation. To accomplish this, the text first in- troduces the theory of operation of the digital logic and then implements the design in integrated circuit form (see Figure P–1). Once the fixed-function IC logic is thoroughly explained, the next step is to implement the design as a graphic design file and then to implement it using the VHDL hardware descriptive language, all within the free version of the Altera Quartus®II development software. Several examples are used to bolster the student’s understanding of the subject before moving on to system-level design and troubleshooting applications of the logic. This step-by-step method has proven over the years to be the most effective method to build the fundamental understanding of digital electronics before proceeding to implement the logic design in VHDL. The Altera Quartus®II software is a free download that allows students to either graphically design their circuit by drawing the logic (using logic gates or 7400 macro- functions) or use VHDL to define their logic. The design can then be simulated on a PC before using the same software to download the logic to an FPGA on one of the commercially available FPGA programmer boards, such as the Altera DE2 illustrated in this text.

基于VHDL的秒表计数器，12864液晶显示，基于ISE的开发平台

VHDL 24进制计数器，VHDL语言编写

倒计时报警 四短一长报警声 daojishi:PROCESS(CLK,EN) VARIABLE L:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF CLK'EVENT AND CLK='1' THEN ----10秒倒计时 IF EN='0' THEN IF L=0 THEN S<='1'; ---超时连续报警 ELSE L:=L-1; S<='0'; END IF; ELSE S<='0'; L:="1001"; END IF; END IF; CASE L IS

文中利用可编程门阵列（FPGA）技术的可重构性与灵活性，设计实现曼彻斯特编解码器。通过FPGA分别实现曼彻斯特编解码器的信号产生，编码部分，解码部分3个模块。采用硬件描述语言VHDL完成了编解码器模块设计，使用Quartus II软件和Modelsim软件进行对编译码器进行相应功能仿真及时序仿真。结果表明，所设计的曼彻斯特编译码器的数据传输具有强抗干扰能力，高传输速率，该过程也具有较高的可靠性。

利用vhdl编写的除法器 精度可调 原理易懂

VHDL for Logic Synthesis, 3rd Edition PDF

基于Quartus II设计一款计算器通过数码管显示

RISC-V处理器 5阶段流水线架构 硬件设计 编译和模拟要求 sudo apt-get install ghdl gtkwave 综合要求 演练 演练将vhdl转换为verilog文件 （需要使用yosys进行synthesys） 放置和布线要求 演练 模拟 “ tb_risc_abs.vhd”是架构的测试平台。 可以通过运行gtkwave risc_v_abs.vcd看到该模拟。 编译设计 运行tb_script文件，将使用ghdl分析整个体系结构的文件。 默认情况下，将在主目录中创建一个名为“ risc_v_abs.vcd”的vcd文件。 综合系统 vhdl代码使用vhd2vl在verilog文件中转换。 使用verilog文件，可以使用yosys完成yosys 。 目标FPGA平台是ICE40 ，您可以使用yosys并使用以下yosys进行更改： synth_<targ