搜索【FPGA、Verilog】的结果

FPGA串口通信（Verilog编写）

2021-11-25 09:05:16 5.31MB FPGA verilog

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基于verilog的AES加密算法

---基于verilog语言的AES时序加密算法，其中包含源代码、仿真文件，加密正确性已通过验证----

2021-11-23 22:42:21 7KB FPGA verilog AES

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Verilog编写的信道估计

2021-11-22 22:31:39 3KB FPGA Verilog 信道估计

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Verilog基本电路设计.docx

包括：时钟域同步、无缝切换、异步FIFO及其实现方法、去抖滤波等电路的设计汇总，希望大家喜欢！！！

2021-11-22 17:06:27 107KB FPGA VERILOG

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勇敢的芯伴你玩转Altera FPGA-吴厚航

本书使用Altera公司的Cyclone Ⅳ FPGA器件，由浅入深地引领读者从板级设计、基础入门实例、FPGA片内资源应用实例和综合进阶实例等方面，玩转FPGA逻辑设计。本书基于特定的FPGA实验平台，既有足够的理论知识深度作支撑，也有丰富的例程供实践学习，并且穿插了笔者在多年FPGA学习和开发过程中所积累的经验和技巧。无论对于希望快速掌握Verilog语言进行FPGA开发的初学者，还是希望快速掌握基于Altera Cyclone Ⅳ FPGA进行开发的设计者，本书都是很好的选择。

2021-11-22 12:22:39 200MB fpga verilog

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四线八拍的步进电机驱动

四线八拍步进电机的基于FPGA驱动的verilog程序代码，其实步进电机的驱动都差不多，按照线圈通电时序就可以完成正转反转了

2021-11-17 11:09:57 4KB 步进电机 fpga verilog 四线八拍

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Bmp To Mif 转换器

Bmp To Mif 转换器 // (karimov 2005) // This program was originnaly written by one of the ECE241 students to convert an image // supplied in a BMP file into an MIF file format for use with Quartus II. // // This program has recently been modified to work with the new VGA controller used with the DE2 // board. // // What to do: // 1. Create an image in Microsoft paint (or other program). The image must be 160 pixels wide, 120 pixels high and // use 24-bits to represent colour information. // 2. Once you create the image you need, flip it up-side down. Then save the BMP file. (example: foo.bmp) // 3. Run this converter in command prompt using the name of the BMP file you created as a command-line parameter. // For example: // bmp2mif foo.bmp // 4. The program generates two files: // image.colour.mif - an MIF file with 3 bits colour information obtained from the BMP file you supplied // image.mono.mif - an MIF file containing 1 bit of colour for every pixel on the screen. The dot will either be // black or white. // You can change the file names once they are created, but they should still have the .mif extension. // // 5. Copy the proper MIF file to the directory where your design is located and include it in your project. // 6. Change the BACKGROUND_IMAGE parameter of the VgaAdapter to indicate your MIF file. // 7. The COLOR_CHANNEL_DEPTH parameter must be set to 1 to work with the image.colour.mif file. #include #include #define FLIP_INT(c) ((c >> 24) & 0x000000FF) | ((c & 0x00FF0000) >> 8) | ((c & 0x0000FF00) << 8) | ((c & 0x000000FF) <> 8) | ((c & 0x00FF) << 8) typedef struct s_header { unsigned short bfType; unsigned int bfSize; unsigned short reserved1; unsigned short reserved2; unsigned int offset; } t_bmp_header; typedef struct s_bmp_info { unsigned int biSize; unsigned int biWidth; unsigned int biHeight; unsigned short biPlanes; unsigned short biBitCount; unsigned in

2021-11-15 21:54:08 27KB DE2 FPGA Verilog BMP

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基于 Verilog 的 PIC16C57 RISC CPU 设计.rar

这是一个基于 Microchip PIC16C57 功能实现的 RISC CPU 设计。指令系统采用了精简指令集架构，指令集数量为 33 个，总线结构采用了数据总线（8 位）和指令总线（12 位）独立分开的哈佛架构。通过搭建仿真平台和编写测试程序，验证了本设计能够正确地执行一系列的测试任务。

2021-11-14 22:09:49 14KB FPGA Verilog RISC CPU

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数电课设FPGA数字密码锁.rar

数电课设，FPGA 电子密码锁，mine中是整个项目过程，password.v 是顶层文件。采用了ps2键盘，lcd1602；report是项目报告，latex写的。

2021-11-14 18:28:20 5.86MB FPGA verilog

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Verilog实现千兆以太网以及ADDA转换

该压缩包包含发送端和接收端，以及ADDA转换，还有以太网组帧等，平台是Verilog，quartus15.0，cyclone5配置。

2021-11-14 15:29:06 8.18MB fpga Verilog ADDA 千兆以太网

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