QuartusII 11.0联合Modelsim仿真 演示，讲得很详细，内有源程序

Matlab代码verilog ECG信号处理使用ModelSim 由于肺音和EMG，使用传感器获取的ECG信号会产生很大的噪音。 可以通过使用大于10的Notch / Peak滤波器来消除由肺部音，EMG引起的噪声，在信号处理器中实施FPGA将使它们大大提高速度。 MATLAB生成8位数据形式的ECG信号。 滤波器系数是使用MATLAB生成的。 离散时间FIR滤波器是使用Verilog代码设计的，可以消除噪声。

学习fpga 用 modelsim 仿真 的很有帮助

modelsim6，年代有些远，但我找的时候其他的也不好找

modelsim10.1a 安装包 Modelsim工具主要用于Verilog编程和仿真，Verilog 在集成电路中主要是用于写CPLD逻辑和FPGA逻辑。modelsim是个仿真工具，做前端设计的写Verilog或VHDL代码，然后能仿真运行！

The newer version of ModelSim SE Reference Manual, for the version 6.3f It lists the explanation of all commands into details.

Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

设计了一个双口RAM，数据口使用inout进行处理，testbench里对数据口进行了仿真，仿真结果已经通过modelsim

Quartus ii 13.0 与 Verilog实现8位计数器，Modelsim仿真，有testbench。

quartus II modelsim 破解安装教程！