vhdl设计的秒表程序
含有三个子模块
CNT10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT10 is
port(count:out std_logic_vector(3 downto 0);
cout:out std_logic;
cin,rst,clk:in std_logic);
end CNT10;
architecture behavioral of CNT10 is
signal counter:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='1'then counter<="0000";cout<='0';
elsif clk'event and clk='1' then if cin='1' then
if counter="1001"then counter<="0000";cout<='1';
else counter<=counter+"0001"; cout<='0';
end if;
end if;
end if;
end process;
count<=counter;
end behavioral;
CNT6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT6 is
port(count:out std_logic_vector(3 downto 0);
cout:out std_logic;
cin,rst,clk:in std_logic);
end CNT6;
architecture behavioral of CNT6 is
signal counter:std_logic_vector(2 downto 0);
begin
process(clk,rst)
begin
if rst='1'then counter<="000";cout<='0';
elsif clk'event and clk='1' then if cin='1' then if counter="101"then counter<="000";cout<='1';
else counter<=counter+"001"; cout<='0';
end if;
end if;
end if;
end process;
count(2 downto 0)<=counter;
count(3)<='0';
end behavioral;
CLKGEN
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CLKGEN is
port(CLK:in std_logic;
NEWCLK:out std_logic);
end CLKGEN;
architecture one of CLKGEN is
SIGNAL CNTER:INTEGER RANGE 0 TO 16#270F#;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF CNTER=16#270# THEN CNTER<=0;
ELSE CNTER<=CNTER+1;
END IF;
END IF;
END PROCESS;
PROCESS(CNTER)
BEGIN IF CNTER =16#270F# THEN NEWCLK<='1';
ELSE NEWCLK<='0';
END IF ;
END PROCESS;
END one;
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