AHB-APB_Bridge_UVM_Env AHB-APB UVM验证环境
2021-08-17 20:58:48 26KB SystemVerilog
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数字IC验证初学入门者,UVM验证方法学,异步FIFO
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uvm+vcs+verdi基本平台搭建,也许平台不是很难,但是网上没有 UVM 在 VCS 中的详细教程,但是对于初学者就是一道屏障,我探索了几天,下文将一步一步的举例子说明 UVM+VCS+Verdi 的 liunx 平台搭建过程
2021-08-12 09:11:09 9.64MB UVM 数字芯片验证 UVM VCS VERDI
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Marshall_UVM - 副本.rar
2021-08-12 09:04:46 255.54MB ssm
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UVM-1.2标准的参考手册,在阅读uvm-1.2源码源码时结合起来看更便于理解
2021-08-10 21:12:45 7.57MB UVM 1.2 Manual
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uvm的cookbook,作为UVM 入门的书籍很不错,推荐给大家,希望大家会喜欢。
2021-08-09 19:19:57 6.22MB UVM
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代码在书里有,其中注释是我自己加的,对应博文里的讲解。
2021-08-05 20:03:13 14KB UVM 数字IC验证
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代码在书里有,其中注释是我自己加的,对应博文里的讲解。
2021-08-05 20:03:13 46KB UVM 数字IC验证
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代码在书里有,其中注释是我自己加的,对应博文里的讲解。
2021-08-05 20:03:13 47KB UVM 数字IC验证
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MENTOR GRAPHICS UVM/OVM DOCUMENTATION VERIFICATION METHODOLOGY ONLINE COOKBOOK Table of Contents Articles Introduction Cookbook/Introduction Cookbook/Acknowledgements Testbench Architecture Testbench/Overview Testbench/Build Testbench/Blocklevel Testbench/IntegrationLevel Component Agent Phasing/Overview Factory UsingFactoryOverrides SystemVerilogPackages Connections to DUT Interfaces Connect/Dut Interface SVCreationOrder Connect/SystemVerilogTechniques ParameterizedTests Connect/Virtual Interface Config/VirtInterfaceConfigDb Connect/VirtInterfacePackage Connect/VirtInterfaceConfigPkg Connect/TwoKingdomsFactory VirtInterfaceFunctionCallChain BusFunctionalModels ProtocolModules Connect/AbstractConcrete Connect/AbstractConcreteConfigDB Configuring a Test Environment Config/Overview Resources/config db Config/Params Package Config/ConfiguringSequences ResourceAccessForSequences MacroCostBenefit Analysis Components & Techniques Analysis/Overview AnalysisPort AnalysisConnections MonitorComponent Predictors Scoreboards CoverageCollectors CoverageModelSwap MetricAnalyzers PostRunPhases End Of Test Mechanisms EOT/Overview Objections Sequences Sequences/Overview Sequences/Items Transaction/Methods Sequences/API Connect/Sequencer Driver/Sequence API Sequences/Generation Sequences/Overrides Sequences/Virtual Sequences/Hierarchy Driver/Use Models Driver/Unidirectional Driver/Bidirectional Driver/Pipelined Sequences/Arbitration Sequences/Priority Sequences/LockGrab Stimulus/Signal Wait Stimulus/Interrupts Sequences/Stopping Sequences/Layering Register Abstraction Layer Registers/Overview Registers/Specification Registers/Adapter Registers/Integrating Registers/Integration Registers/Register
2021-08-03 16:35:53 9.13MB UVM OVM Verification Methodology
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