ICN6201 /02 is a bridge chip which receives MIPI DSI inputs and sends LVDS outputs.
MIPI DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input
bandwidth is 4Gbps ; and the MIPI defined ULPS(ultra - low -power state) is also supported . ICN6201 decodes
MIPI DSI 18bepp RGB666 and 24bpp RGB888 packets.
The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.
ICN6201 /02 support video resolution up to FHD (1920x1080) and WUXGA (1920x1200).
ICN6201 adopts QFN48 package and ICN6202 adopts QFN40 package.
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