这是从外网好不容易找到的，上传与大家共享，不要积分随便下！我也是下载的，不是自己发明的，如果再去要下载积分，人品还不至于这么差！ 里面有加密的，官方说明是这样的：There are two encrypted verilog files in the "DE2_70_TV_PIP" demonstraction. If users want to modify this demonstration and re-compile the project, please perform the following steps: 1.Use Notepad or other text edit software to open the file "Teraisc_license.dat", which is located in the "DE2_70_demonstrations/License for encrypted IP" folder of the DE2-70 System CD-ROM. 2. The license contains the FEATURE lines required to license the IP Cores as shown below FEATURE 535C_0009 alterad 9999.12 permanent uncounted D702CF471AC0 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="0F45 927A 00F9 DBF3 3AAB D703 4F3D 2406 B374 \ 0E5C 87A1 34BA 10C6 0C08 E554 183B BD2D B79D D64E 3F98 393E \ 94FB F798 07B8 C334 C8B6 D1E4 36F5 67D5 1690" FEATURE 535C_000A alterad 9999.12 permanent uncounted F7FD875F1A28 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="1834 5F1A 9CE6 15FD 9246 A640 66FE 918D 1091 \ A2D0 7DF8 7584 0E78 3732 1F48 0B24 3A92 870A EDAA F6F0 2145 \ 3098 5631 C5E1 4DC2 B14D C81A D30D 5518 63D0" 3.Open your Quartus II license.dat file in a text editor. 4.Copy the all the contents of the Terasic_license.dat and paste it at the end of your Quartus II license file. (Note: Do not delete any FEATURE lines from the Quartus II license file. Doing so will result in a non-usable license file.) 5.Open the "DE2_70_TV_PIP" project from Quartus II and compile this project. 6.After compilation is completed, it will generate a sof file named "DE2_70_TV_PIP_time_limited.sof" 7.Load this sof file into the FPGA and the demonstration will have at most one hour to be modified. In another words, the VGA output will be turned off after one hour. If users want to know more information about this demonstration, please contact us at support@terasic.com.

DE2-70 资源（含源码）

de2-70 camera 亲测可用

连接已经失效，资料更新中......................

FPGA开发板DE2-70的使用方式，方便初学者进行入门学习。

DE2-70引脚分配表 DE2-70引脚分配表 DE2-70引脚分配表

详细的引脚说明，FPGA开发分配引脚时需要用到。

de2-70 + ov7670的所有图像采集的verilog源代码

uart fpga 源代码，基于DE2-70调试过的，可通过串口小助手调试，祝你成功

这是DE2-70开发板上的7个典型程序实例，主要基于verilog 语言编写